`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: Abu liu
// 
// Create Date: 2020/05/05 16:15:03
// Design Name: global_sync
// Module Name: global_sync
// Project Name: 
// Target Devices: xc7z020
// Target Board: zedboard
// Tool Versions: vivado 2019.1
// Description: Top entity of udp send module
// 
// Dependencies:
// 			
// 			
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////

module global_sync (
    input   xtal_clk,       //external crystal clock, 100 Mhz in default
    input   ext_rstn,       //external async reset signal, low effictive

    output  pll_clk_50mhz,  //pll clock out, 50 Mhz
    output  pll_clk_100mhz, //pll clock out, 100 Mhz
    output  pll_clk_125mhz, //pll clock out, 125 Mhz
    output  sys_sync_rstn   //syncronized reset signal, low effictive
);

reg rst_reg1;
reg rst_reg2;

always @ (posedge )

endmodule